Target architecture determination

ABSTRACT

Examples of the present disclosure provide apparatuses and methods for target architecture determination. An example method comprises receiving an indication of a type of target architecture in a portion of source code and creating compiled code for the type of target architecture based on the indication.

PRIORITY INFORMATION

This application is a Continuation of U.S. application Ser. No. 16/199,477, filed Nov. 26, 2018, which issues as U.S. Pat. No. 10,795,653 on Oct. 6, 2020, which is a Continuation of U.S. application Ser. No. 15/097,764, filed Apr. 13, 2016, which issued as U.S. Pat. No. 10,140,104 on Nov. 27, 2018, which claims the benefit of U.S. Provisional Application No. 62/147,341, filed Apr. 14, 2015, the contents of which are included herein by reference.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor memory apparatuses and methods, and more particularly, to apparatuses and methods related to target architecture determination.

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.

Electronic systems often include a number of processing resources (e.g., one or more processors), which may retrieve and execute instructions and store the results of the executed instructions to a suitable location. A processor can comprise a number of functional units (e.g., herein referred to as functional unit circuitry such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and/or a combinatorial logic block, for example, which can execute instructions to perform logical operations such as AND, OR, NOT, NAND, NOR, and XOR logical operations on data (e.g., one or more operands).

A number of components in an electronic system may be involved in providing instructions to the functional unit circuitry for execution. The instructions may be generated, for instance, by a processing resource such as a controller and/or host processor. Data (e.g., the operands on which the instructions will be executed to perform the logical operations) may be stored in a memory array that is accessible by the functional unit circuitry. The instructions and/or data may be retrieved from the memory array and sequenced and/or buffered before the functional unit circuitry begins to execute instructions on the data. Furthermore, as different types of operations may be executed in one or multiple clock cycles through the functional unit circuitry, intermediate results of the operations and/or data may also be sequenced and/or buffered.

In many instances, the processing resources (e.g., processor and/or associated functional unit circuitry) may be external to the memory array, and data is accessed via a bus between the processing resources and the memory array to execute a set of instructions. Processing performance may be improved in a processor-in-memory (PIM) device, in which a processor may be implemented internal and/or near to a memory (e.g., directly on a same chip as the memory array). A PIM device may save time by reducing and/or eliminating external communications and may also conserve power. Data can be moved from the memory array to registers external to the memory array via a bus.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an apparatus in the form of a computing system including a memory device in accordance with a number of embodiments of the present disclosure.

FIG. 2 illustrates a block diagram of a heterogeneous target architecture system in accordance with a number of embodiments of the present disclosure.

FIG. 3 illustrates examples of source code for heterogeneous target architecture determination in accordance with a number of embodiments of the present disclosure.

FIG. 4 illustrates a table showing address space indicators and target architectures in accordance with a number of embodiments of the present disclosure.

DETAILED DESCRIPTION

Examples of the present disclosure provide apparatuses and methods for target architecture determination. An example method comprises receiving an indication of a type of target architecture in a portion of source code and creating compiled code for the type of target architecture based on the indication.

Computing architectures can include a variety of hardware and software configurations that can perform a variety of computing functions. The code that the various computing architectures can execute to perform their functions can vary among the various computing architectures. Therefore, code can be created for execution by a particular computing architecture (e.g., target architecture). The code for the target architecture can include instructions that are unique and/or particular to a target architecture.

In a number of embodiments, code for a target architecture can include sets of instructions that are specific to a particular target architecture, therefore code can be generated that use instructions specific to a target architecture. The code that is generated for a particular target architecture can be executed properly by the particular target architecture, but another target architecture may not be able to execute the code and/or may generate errors when executing the code. A target architecture that executes code with instructions that are specific to a particular target architecture can be a heterogeneous target architecture. A target architecture that executes code with instructions that are not specific to a particular target architecture can be a homogeneous target architecture.

In a number of embodiments, source code can include an attribute that indicates a type of target architecture for a portion of instructions in the source code by using a named address space that is associated with a type of target architecture. For example, source code can include a named address space that a compiler will recognize and create compiled code (e.g., assembly code and/or object code) for the type of target architecture indicated by the named address space. Also, source code can include a number of portions of source code that define attributes that include named address spaces. Compiled code can be created by a compiler for each of the portions of source code according to the type of target architecture indicated by the named address spaces.

In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, “a number of” a particular thing can refer to one or more of such things (e.g., a number of memory arrays can refer to one or more memory arrays).

The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 270 may reference element “70” in FIG. 2, and a similar element may be referenced as 370 in FIG. 3. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate certain embodiments of the present invention, and should not be taken in a limiting sense

FIG. 1 is a block diagram of an apparatus in the form of a computing system 100 including a target architecture (e.g., memory device 120) in accordance with a number of embodiments of the present disclosure. The target architecture in FIG. 1 is a memory device 120. In a number of embodiments, target architectures can be memory devices (e.g., a PIM capable device), graphics processing units (GPUs), digital signal processors (DSPs), field programmable gate arrays (FPGAS), among other types of target architectures. As used herein, a memory device 120, a memory array 130, controller 140, complier 114, and/or sensing circuitry 150 might also be separately considered an “apparatus.”

System 100 includes a host 110 coupled to memory device 120, which includes a memory array 130. System 100 can be a PIM capable system. Host 110 can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, or a memory card reader, among various other types of hosts. Host 110 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system 100 can include separate integrated circuits or both the host 110 and the device associated with a type of target architecture, memory device 120 in FIG. 1, can be on the same integrated circuit. The device associated with a type of target architectures that is part of system 100 and coupled to host 110 can be memory devices, graphics processing units (GPUs), digital signal processors (DSPs), field programmable gate arrays (FPGAS), The system 100 can be, for instance, a server system and/or a S performance computing (HPC) system and/or a portion thereof. Although the example shown in FIG. 1 illustrates a system having a Von Neumann architecture, embodiments of the present disclosure can be implemented in non-Von Neumann architectures (e.g., a Turing machine), which may not include one or more components (e.g., CPU, ALU, etc.) often associated with a Von Neumann architecture.

The host 110 can include a processor 112 and a compiler 114. Processor 112 can comprise a number of functional units such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and/or a combinatorial logic block, for example, which can comprise a number of registers and can be used to execute instructions by performing logical operations such as AND, OR, NOT, NAND, NOR, and XOR logical operations on operands. For example, the number of functional units, which may be referred to as functional unit circuitry, may be used to perform arithmetic operations such as addition, subtraction, multiplication, and/or division on operands. In many instances, the processing resources may be external to memory device 120 comprising memory array 130 in which the instructions to be executed (e.g., the executable file) are stored. The instructions to be executed can be accessed (e.g., retrieved from the memory array 130) via a bus 154 between the processor 112 and the memory device 120, for example.

Compiler 114 can include a non-transitory computer readable medium that stores instructions executable by processor 112 to perform various embodiments of the present disclosure. For example, compiler 114 can include instructions to identify target architectures and to create compile code for particular types of target architectures. Also, compiler 114 can include a table that correlates named address spaces with types of target architectures.

Compiler 114 can receive source code and use the processor 112 to generate compiled code based on the source code. The compiler 114 can include instructions stored on a non-transitory computer readable medium that can be executed by the processor to generate the compiled code. Compiler 114 can recognize commands from the source code that are associated with a particular architecture and create compiled code for the particular architecture.

For clarity, the system 100 has been simplified to focus on features with particular relevance to the present disclosure. The memory array 130 can be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, processor in memory (PIM) array, RRAM array, NAND flash array, and/or NOR flash array, for instance. The array 130 can comprise memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digit lines or data lines). Although a single array 130 is shown in FIG. 1, embodiments are not so limited. For instance, memory device 120 may include a number of arrays 130 (e.g., a number of banks of DRAM cells). An example DRAM array is described in association with FIGS. 2 and 3.

The memory device 120 includes address circuitry 142 to latch address signals provided over an I/O bus 156 (e.g., a data bus) through I/O circuitry 144. Address signals are received and decoded by a row decoder 146 and a column decoder 152 to access the memory array 130. Data can be read from memory array 130 by sensing voltage and/or current changes on the sense lines using sensing circuitry 150. The sensing circuitry 150 can read and latch a page (e.g., row) of data from the memory array 130. The I/O circuitry 144 can be used for bi-directional data communication with host 110 over the I/O bus 156. The write circuitry 148 is used to write data to the memory array 130.

Controller 140 decodes signals provided by control bus 154 from the host 110. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control operations (e.g., PIM operations) performed on the memory array 130, including data read, data write, and data erase operations. In various embodiments, the control circuitry 140 is responsible for executing instructions from the host 110. The controller 140 can be a state machine, a sequencer, or some other type of controller.

In a number of embodiments, the sensing circuitry 150 can comprise a number of sense amplifiers and a number of compute components, which may comprise a latch serving as a Comp Compulator and can be used to perform logical operations (e.g., on data associated with complementary sense lines).

FIG. 2 illustrates a block diagram of a heterogeneous target architecture system in accordance with a number of embodiments of the present disclosure. In FIG. 2, source code 260 illustrates an example portion of source code that can be used to determine a type of target architecture for the instruction in the source code. Source code 260 defines an attribute 271 that includes a named address space 270 to indicate the type of target architecture for the instructions of this portion of the source code 260. The named address space 270 can include an integer to indicate on which type of target architecture the instructions will be used. The address space 270 in FIG. 2 is address space “102”. The various target architectures can include graphics processing units (GPUs), processor in memory (PIM) devices, digital signal processors (DSPs), field programmable gate arrays (FPGAS), among other architectures. Also, a named address space can be assigned to various versions of an architecture. For example, a first named address space can be assigned to a PIM device having a first storage capacity and a second named address space can be assigned to PIM device having a second storage capacity. Also, a first named address space can be assigned to horizontal operations on a PIM device and a second named address space can be assigned to vertical operations on a PIM device. Each of the devices having a different architecture can be coupled via a host that includes a host processor, such as processor 112 in FIG. 1. The attribute can also include variable 272. Variable 272, indicated as “MyVariable” in FIG. 2, can be associated with the instructions for the portion of the source code that has named address space 270.

In FIG. 2, a compiler 262 can receive and interpret the source code 260. The compiler 262 can include parser 266 to separate the source code in a number of portions based on the named address space of the source code 260. The parser 266 can use a number of rules, which are described below in association with FIG. 3, to group portions of source code together that can be compiled into compiled code for a particular architecture indicated by the named address space. For example, parser 266 can separate the source code 260 from other portions of source code (not shown) based on the named address space 270 of the source code, which indicates source code 260 is for the type of target architecture indicated by named address space “102”.

Once the parser 266 has separated the source code based on the named address spaces of the source code, the target identifier 268 can determine which target architecture is associated with the named address space 270 of the source code 260. The target identifier 268 can use a table, such as table 495 from FIG. 4 and described below in association with FIG. 4, to correlate the type of target architecture associated with the named address space 270. Code generator 270 can include instructions for creating compiled code that is specific for the various target architectures associated with a named address space 270. In FIG. 2, the address space “102” is associated with “Architecture_X”, therefore code generator 270 can create compiled code that includes instructions for the target architecture of “Architecture_X”.

Once the target identifier 268 has identified the target architecture for the source code, the code generator 270 can create compiled code for the instructions from the source code. The code generator 270 can create compiled code 264 and compiled code 266. The compiled code 264 can include instructions for a base processor. The source code (not shown) from which the compiled code 264 was created can include an address space indicator of “0” or not include an address space indicator. The compiled code 266 can include instructions for Architecture_X, as indicated by named address space 270 in source code 260. Code generator 270 can include instructions for creating code that is specific for the various target architectures associated with an address space indicator 270.

FIG. 3 illustrates examples of source code for target architecture determination in accordance with a number of embodiments of the present disclosure. Examples 380, 382, and 384 in FIG. 3 each include example of source code that can be compiled according to a number of embodiments of the present disclosure. Example 380 illustrates source code that can be compiled together because the attributes include named address spaces that are associated with the same type of target architecture. Example 382 illustrates source code that can be compiled into two separate portions of compiled code because the attributes include named address spaces that are associated with different types of target architectures. Example 384 illustrates source code that includes complex flow control statements that can be compiled together because the attribute includes a single named address space associated with a particular type of target architecture.

In example 380, attributes 371-1 and 371-2 both include named address space 370-1, defined by integer “102”. Therefore, source code portion 381 having variables 372-1 and 372-2 in the argument, both associated with named address space 370-1, can be compiled together into compiled code that uses instructions associated with a type of target architecture correlated to named address space “102”. The source code in example 380 includes a first attribute 371-1 with address space indicator 370-1, which is “102” in FIG. 3, having an associated variable 372-1, which is “XX” in FIG. 3; and a second attribute 371-2 with address space indicator 370-1, which is “102” in FIG. 3, having an associated variable 372-2, which is “YY” in FIG. 3. In example 380, the first attribute 371-1 and the second attribute 371-2 both have the same address space indicator 370-1, therefore the source code portion 381 can be compiled together by a compiler into compiled code for the target architecture associated with address space indicator 370-1. The compiled code based on the source code from example 380 can use variables 372-1 and 372-2 defined in the first and second attributes 371-1 and 371-2.

In example 382, attribute 371-3 includes named address space 370-1 and 370-2, defined by integer “102”, and attribute 371-4 includes named address space 370-3, defined by integer “103”. Therefore, source code portion 383 having variables 372-1, 372-2, 372-3, and 372-4 in the argument, associated with named address spaces 370-1 and 370-3, can be compiled into separate portions of compiled code, each using instructions associated with a particular type of target architecture. The source code in example 382 includes a first attribute with address space indicator 370-1, which is “102” in FIG. 3, having associated variables 372-1, which is “X” in FIG. 3, and 372-2, which is “Y” in FIG. 3; and a second attribute with address space indicator 370-3, which is “103” in FIG. 3, having associated variables 372-3, which is “S” in FIG. 3, and 372-4, which is “T” in FIG. 3. In example 382, the first attribute and the second attribute have different address space indicators, 370-1 and 370-3, therefore the source code portion 383 can be compiled by a compiler into two different portions of compiled code. A first portion can be compiled for target architecture associated with address space 370-1 and a second portion can be complied for the target architecture associated with address space 370-3.

In example 384, attribute 371-5 includes named address space 370-1, defined by integer “102”. Source code portion 385 includes complex flow control statements that include variables 372-1 and 372-2 in the argument, both associated with named address space 370-1, can be compiled together into compiled code that uses instructions associated with a type of target architecture correlated to named address space “102”. The source code in example 384 includes a first attribute with address space indicator 370-1, which is “102” in FIG. 3, having associated variables 372-1, which is “X” in FIG. 3, and 372-2, which is “Y” in FIG. 3. In example 384, source code portion 385 includes instructions having complex flow control. In a number of embodiments, when source code that includes complex flow control instructions is associated with a single target architecture, as indicated by an attribute having a single named address space, the source code can be compiled together into compiled code. In example 384, the complex flow control instructions, such as if-then-else statements and switch statements, among others, can be compiled together into compiled code for the target architecture associated with named address space 370-1 in response to the source code associating only named address space 370-1 with the complex flow control instructions in source code portion 385 of example 384.

FIG. 4 illustrates a table showing address space indicators and target architectures in accordance with a number of embodiments of the present disclosure. Table 495 in FIG. 4 can include a named address space 470 and a target architecture 492. In Table 495, named address space 470-1, which is “100” in FIG. 4, can be associated with PIM type 1 492-1 target architecture, named address space 470-2, which is “101” in FIG. 4, can be associated with PIM type 2 492-2 target architecture, named address space 470-3, which is “102” in FIG. 4, can be associated with PIM type 3 492-3 target architecture, and named address space 470-4, which is “0” in FIG. 4, can be associated with host processor 492-4 target architecture. In a number of embodiments, the target architectures that are identified and associated with a named address space can be a number of heterogeneous target architectures that include one or more disparate instruction set architectures (e.g., instructions that are only properly executed by a particular target architecture). Table 495 can be stored in a compiler, such as in the target identifier 268 on compiler 262 in FIG. 2. Table 495 can be used by a compiler to determine which target architecture will be the basis for creating compiled code from source code.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of the one or more embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment. 

What is claimed is:
 1. An apparatus, comprising: a processor; and a compiler that includes: a parser, wherein the parser is configured to separate a source code from other portions of source code based on a named address space defined in the source code; a target identifier, wherein the target identifier is configured to determine a type of target architecture based on the named address space defined in the source code; and a code generator, wherein the code generator is configured to create a first portion of compiled code that includes heterogeneous instructions for the type of target architecture and a second portion of compiled code that includes instructions for a base processor.
 2. The apparatus of claim 1, wherein the parser separates the source code in a number of portions based on a number of named address spaces, including the named address space defined in the source code.
 3. The apparatus of claim 1, wherein the first portion of complied code includes homogeneous instructions for the type of targe architecture.
 4. The apparatus of claim 1, wherein the target architecture is configured to execute only the first portion of compiled code.
 5. The apparatus of claim 1, wherein the processor is configured to execute only the second portion of compiled code
 6. The apparatus of claim 1, wherein the target identifier includes a table correlating the type of the target architecture with the named address space.
 7. A method, comprising: creating a first portion of compiled code that includes instructions for a target architecture, wherein the first portion of compiled code includes a number of heterogeneous instructions for the target architecture; and creating a second portion of compiled code that includes instructions for a base processor, wherein the second portion of compiled code includes a number of homogeneous instructions and a number of heterogenous instructions for the base processor.
 8. The method of claim 7, further including executing the first portion of complied code by the target architecture.
 9. The method of claim 7, further including executing the second portion of compiled code with the base processor.
 10. The method of claim 7, wherein creating the first portion of compiled code includes separating a source code from other portions of source code based on a named address space defined in the source code.
 11. The method of claim 10, wherein creating the first portion of compiled code includes determining a type of target architecture based on the named address space defined in the source code.
 12. The method of claim 10, wherein the named address space includes an integer to indicate the type of the target architecture.
 13. The method of claim 7, wherein the first portion of compiled code includes the number of homogeneous instructions.
 14. The method of claim 7, further comprising creating a third portion of compiled code that includes instructions for a different target architecture.
 15. The method of claim 14, wherein the third portion of compiled code is created in response to the source code having different address spaces.
 16. The method of claim 7, wherein the target architecture is a processing in memory (PIM) architecture.
 17. An apparatus comprising: a processor; and a compiler that includes: a parser, wherein the parser is configured to separate a source code from other portions of source code based on a named address space defined in the source code and to group portions of the source code together based on type of target architecture; a target identifier, wherein the target identifier is configured to determine a target architecture based on the named address space of the source code; and a code generator, wherein the code generator is configured to create a first portion of compiled code from the source code that includes instructions for the target architecture and wherein the target architecture is configured to execute the first portion of compiled code.
 18. The apparatus of claim 17, wherein the first portion of compiled code include a number of heterogeneous instructions for the target architecture and a number of homogeneous instructions.
 19. The apparatus of claim 17, wherein the code generator is configured to create a second portion of compiled code from the source code that includes instructions for a base processor.
 20. The apparatus of claim 19, wherein the base processor is configured to execute the second portion of compiled code. 